Performance analysis of fully-adaptable CRC accelerators on an FPGA

Amila Akagic, Hideharu Amano

研究成果: Conference contribution

抄録

We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.

本文言語English
ホスト出版物のタイトルProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
ページ575-578
ページ数4
DOI
出版ステータスPublished - 2012 12 12
イベント22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
継続期間: 2012 8 292012 8 31

出版物シリーズ

名前Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
国/地域Norway
CityOslo
Period12/8/2912/8/31

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用

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