Performance, cost, and power evaluations of on-chip network topologies in FPGAs

Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

研究成果: Conference contribution

抄録

On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.

本文言語English
ホスト出版物のタイトルProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
ページ181-189
ページ数9
出版ステータスPublished - 2010 7月 20
イベント9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
継続期間: 2010 2月 162010 2月 18

出版物シリーズ

名前Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
国/地域Austria
CityInnsbruck
Period10/2/1610/2/18

ASJC Scopus subject areas

  • 計算理論と計算数学
  • コンピュータ ネットワークおよび通信
  • ソフトウェア

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