Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

Noriaki Suzuki, Hideharu Amano

研究成果: Conference contribution

抄録

The instruction set architecture of MBP-light, a dedicated processor for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype. The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster. Only a special instruction for hashing cluster address is efficient and improves the performance with 2.80%, but other special instructions are almost useless. It appears that the dominant operations in the DSM management program are handling packet queues assigned into the local cluster. Thus, common RISC instructions, especially load/store instructions, are frequently used. Separating instruction and data memory improves performance with 33%. The results-suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous.

本文言語English
ホスト出版物のタイトルProceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003
編集者H.R. Arabnia, Y. Mun, H.R. Arabnia, Y. Mun
ページ1155-1161
ページ数7
出版ステータスPublished - 2003 12 1
イベントProceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications - Las Vegas, NV, United States
継続期間: 2003 6 232003 6 26

出版物シリーズ

名前Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications
3

Other

OtherProceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications
国/地域United States
CityLas Vegas, NV
Period03/6/2303/6/26

ASJC Scopus subject areas

  • 工学(全般)

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