Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano

研究成果: Conference contribution

抄録

Ethernet has been used for interconnection networks of high-performance computing (HPC) systems that include PC clusters. Although a layer-2 Ethernet topology is limited to a tree structure in order to avoid broadcast storms and deadlocks of frames, various topologies with deadlock-free routing, that include loops, suitable for parallel processing can be used by the application of IEEE 802.1Q VLAN technology. However, their performance and power evaluations on real PC clusters with Ethernet have been rarely done. Thus, their evaluation on real PC clusters with Ethernet is important to analyze their impact on the total systems and validate their simulation results. In this paper, firstly we measure tree, and fully connected topologies with link aggregation on a 66-node/528-core PC cluster with a number of Ethernet switches. Secondly, we measure the optimization of the power consumption of Ethernet by a power-aware link regulation in order to reduce the power consumption of Ethernet switches on a real PC cluster. Measurement results show that the fully connected topology achieves 3.21 TFlops in High-Performance Linpack Benchmark (HPL), and its Rmax/Rpeak value is 67%. Up to 23% of the power consumption of networks can be reduced by the power-aware link regulation, while the performance is degraded by less than 1%.

元の言語English
ホスト出版物のタイトルProceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011
ページ50-57
ページ数8
DOI
出版物ステータスPublished - 2011
イベント2nd International Conference on Networking and Computing, ICNC 2011 - Osaka, Japan
継続期間: 2011 11 302011 12 2

Other

Other2nd International Conference on Networking and Computing, ICNC 2011
Japan
Osaka
期間11/11/3011/12/2

Fingerprint

Ethernet
Topology
Electric power utilization
Switches
Agglomeration
Processing

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications

これを引用

Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H., & Amano, H. (2011). Performance evaluation of power-aware multi-tree ethernet for HPC interconnects. : Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011 (pp. 50-57). [6131793] https://doi.org/10.1109/ICNC.2011.17

Performance evaluation of power-aware multi-tree ethernet for HPC interconnects. / Koibuchi, Michihiro; Watanabe, Takafumi; Minamihata, Atsushi; Nakao, Masahiro; Hiroyasu, Tomoyuki; Matsutani, Hiroki; Amano, Hideharu.

Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. 2011. p. 50-57 6131793.

研究成果: Conference contribution

Koibuchi, M, Watanabe, T, Minamihata, A, Nakao, M, Hiroyasu, T, Matsutani, H & Amano, H 2011, Performance evaluation of power-aware multi-tree ethernet for HPC interconnects. : Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011., 6131793, pp. 50-57, 2nd International Conference on Networking and Computing, ICNC 2011, Osaka, Japan, 11/11/30. https://doi.org/10.1109/ICNC.2011.17
Koibuchi M, Watanabe T, Minamihata A, Nakao M, Hiroyasu T, Matsutani H その他. Performance evaluation of power-aware multi-tree ethernet for HPC interconnects. : Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. 2011. p. 50-57. 6131793 https://doi.org/10.1109/ICNC.2011.17
Koibuchi, Michihiro ; Watanabe, Takafumi ; Minamihata, Atsushi ; Nakao, Masahiro ; Hiroyasu, Tomoyuki ; Matsutani, Hiroki ; Amano, Hideharu. / Performance evaluation of power-aware multi-tree ethernet for HPC interconnects. Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. 2011. pp. 50-57
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