Performance evaluation of SNAIL: A multiprocessor based on the Simple Serial Synchronized Multistage Interconnection Network architecture

Junji Yamamoto, Takashi Fujiwara, Takuji Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano

研究成果: Article査読

4 被引用数 (Scopus)

抄録

Simple Serial Synchronized (SSS)-Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are presented. The heart of SNAIL is a prototype 1 μm CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs at a 50 MHz clock speed. The message combining is implemented with only a 20% increase in hardware. From empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient.

本文言語English
ページ(範囲)1081-1103
ページ数23
ジャーナルParallel Computing
25
9
DOI
出版ステータスPublished - 1999 9月

ASJC Scopus subject areas

  • ソフトウェア
  • 理論的コンピュータサイエンス
  • ハードウェアとアーキテクチャ
  • コンピュータ ネットワークおよび通信
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 人工知能

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