Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida, Toshinori Numata

    研究成果: Article査読

    11 被引用数 (Scopus)

    抄録

    We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

    本文言語English
    論文番号6072236
    ページ(範囲)8-10
    ページ数3
    ジャーナルIEEE Electron Device Letters
    33
    1
    DOI
    出版ステータスPublished - 2012 1

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

    フィンガープリント

    「Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル