Performance improvement methodology for ClearSpeed's CSX600

Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano

研究成果: Conference contribution

5 引用 (Scopus)

抜粋

This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.

元の言語English
ホスト出版物のタイトル2007 International Conference on Parallel Processing, ICPP
DOI
出版物ステータスPublished - 2007 12 1
イベント36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
継続期間: 2007 9 102007 9 14

出版物シリーズ

名前Proceedings of the International Conference on Parallel Processing
ISSN(印刷物)0190-3918

Other

Other36th International Conference on Parallel Processing in Xi'an, ICPP
China
Xi'an
期間07/9/1007/9/14

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)

これを引用

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K., & Amano, H. (2007). Performance improvement methodology for ClearSpeed's CSX600. : 2007 International Conference on Parallel Processing, ICPP [4343884] (Proceedings of the International Conference on Parallel Processing). https://doi.org/10.1109/ICPP.2007.66