Performance improvement methodology for ClearSpeed's CSX600

Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.

本文言語English
ホスト出版物のタイトル2007 International Conference on Parallel Processing, ICPP
DOI
出版ステータスPublished - 2007 12月 1
イベント36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
継続期間: 2007 9月 102007 9月 14

出版物シリーズ

名前Proceedings of the International Conference on Parallel Processing
ISSN(印刷版)0190-3918

Other

Other36th International Conference on Parallel Processing in Xi'an, ICPP
国/地域China
CityXi'an
Period07/9/1007/9/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 工学(全般)

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