Performance improvement technique for synchronous circuits realized as LUT-based FPGA's

Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta

研究成果: Article査読

7 被引用数 (Scopus)

抄録

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 333% for six combination circuits, and 25% for 18 sequential circuits.

本文言語English
ページ(範囲)455-459
ページ数5
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
3
3
DOI
出版ステータスPublished - 1995 9

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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