Performance improvement technique for synchronous circuits realized as LUT-based FPGA's

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 333% for six combination circuits, and 25% for 18 sequential circuits.