We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV th universal line is eliminated by suppressing R SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.
|ホスト出版物のタイトル||IEEE International Reliability Physics Symposium Proceedings|
|出版物ステータス||Published - 2012|
|イベント||2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States|
継続期間: 2012 4 15 → 2012 4 19
|Other||2012 IEEE International Reliability Physics Symposium, IRPS 2012|
|期間||12/4/15 → 12/4/19|
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