Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

    研究成果: Conference contribution

    6 被引用数 (Scopus)

    抄録

    We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV th universal line is eliminated by suppressing R SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

    本文言語English
    ホスト出版物のタイトル2012 IEEE International Reliability Physics Symposium, IRPS 2012
    ページ6A.3.1-6A.3.6
    DOI
    出版ステータスPublished - 2012 9 28
    イベント2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States
    継続期間: 2012 4 152012 4 19

    出版物シリーズ

    名前IEEE International Reliability Physics Symposium Proceedings
    ISSN(印刷版)1541-7026

    Other

    Other2012 IEEE International Reliability Physics Symposium, IRPS 2012
    CountryUnited States
    CityAnaheim, CA
    Period12/4/1512/4/19

    ASJC Scopus subject areas

    • Engineering(all)

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