Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

研究成果: Conference contribution

5 引用 (Scopus)

抜粋

We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV th universal line is eliminated by suppressing R SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

元の言語English
ホスト出版物のタイトルIEEE International Reliability Physics Symposium Proceedings
DOI
出版物ステータスPublished - 2012
外部発表Yes
イベント2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States
継続期間: 2012 4 152012 4 19

Other

Other2012 IEEE International Reliability Physics Symposium, IRPS 2012
United States
Anaheim, CA
期間12/4/1512/4/19

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Saitoh, M., Ota, K., Tanaka, C., Nakabayashi, Y., Uchida, K., & Numata, T. (2012). Performance, variability and reliability of silicon tri-gate nanowire MOSFETs. : IEEE International Reliability Physics Symposium Proceedings [6241864] https://doi.org/10.1109/IRPS.2012.6241864