Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor with the capability of changing its hardware functionality within a clock cycle. While implementing an application on the DRP, designers face the task of selecting how to efficiently use resources in order to achieve particular goals such as to improve the performance, to reduce the power dissipation, or to minimize the resource use. To analyze the impact of trade-off selections on these aspects, the Discrete Cosine Transform (DCT) algorithm has been implemented exploiting various design policies. The evaluation result shows that the performance, cost and consuming power are influenced by the implementation method. For example, the execution time can reduce 17% in case of using the distributed memory against the register files; or up to 40% whether the embedded multipliers are used.

本文言語English
ホスト出版物のタイトルReconfigurable Computing
ホスト出版物のサブタイトルArchitectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers
出版社Springer Verlag
ページ115-121
ページ数7
ISBN(印刷版)9783540367086
DOI
出版ステータスPublished - 2006 1月 1
イベント2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 - Delft, United States
継続期間: 2006 3月 12006 3月 3

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
3985 LNCS
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Other

Other2nd International Workshop on Applied Reconfigurable Computing, ARC 2006
国/地域United States
CityDelft
Period06/3/106/3/3

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • コンピュータ サイエンス(全般)

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