Physical understanding of Vth and Idsat variations in (110) CMOSFETs

Masumi Saitoh, Nobuaki Yasutake, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

    研究成果: Conference contribution

    8 被引用数 (Scopus)

    抄録

    In this paper, the first systematic study of Vth variations (σVth) and Idsat variations (σI dsat) in (110) n/pMOSFETs is presented. σVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σVth in (110) FETs. We also found that σI dsat is determined by both σVth and the degree of velocity saturation. σIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.

    本文言語English
    ホスト出版物のタイトル2009 Symposium on VLSI Technology, VLSIT 2009
    ページ114-115
    ページ数2
    出版ステータスPublished - 2009 11月 16
    イベント2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
    継続期間: 2009 6月 162009 6月 18

    出版物シリーズ

    名前Digest of Technical Papers - Symposium on VLSI Technology
    ISSN(印刷版)0743-1562

    Other

    Other2009 Symposium on VLSI Technology, VLSIT 2009
    国/地域Japan
    CityKyoto
    Period09/6/1609/6/18

    ASJC Scopus subject areas

    • 電子工学および電気工学

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