A hyper-thin SOI memory device that has both conduction channel and storage islands at the lower gate voltage is demonstrated. It shows both Coulomb staircase and oscillations at 20 K. By using coexistence of memory with Coulomb blockade effects, the Coulomb oscillation phase is well controlled. This will open a way to the robust nano-structure devices, including the functional devices for multi-value memory/logic.
|出版ステータス||Published - 1999 12月 1|
|イベント||Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC) - Santa Barbara, CA, USA|
継続期間: 1999 6月 28 → 1999 6月 30
|Other||Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC)|
|City||Santa Barbara, CA, USA|
|Period||99/6/28 → 99/6/30|
ASJC Scopus subject areas