Power Analysis of Directly-connected FPGA Clusters

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano

研究成果: Conference contribution

抄録

Although low power consumption is a significant advantage of FPGA clusters, almost no power analyses with real systems have been reported. This study reports the detailed power consumption analyses of two FPGA clusters, namely, M-KUBOS and FiC, with power measurement tools and real applications. In both clusters, the type of logic design shells determines the base power consumption. For building clusters, the power for node communication links is mainly determined by the number of activated links and not influenced by the number of actually used links. Therefore, applying the link aggregation technique does not affect the power consumption. Increasing the clock frequency of the application logic mildly increases the power consumption. The obtained results suggest that the best way to reduce the total power consumption of an FPGA cluster and improve its performance is to use the minimum number of links for the application, apply link aggregation, and aggressively increase the clock frequency.

本文言語English
ホスト出版物のタイトル25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781665419895
DOI
出版ステータスPublished - 2022
イベント25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Tokyo, Japan
継続期間: 2022 4月 202022 4月 22

出版物シリーズ

名前25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings

Conference

Conference25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022
国/地域Japan
CityTokyo
Period22/4/2022/4/22

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • エネルギー工学および電力技術
  • 電子工学および電気工学
  • 人工知能
  • コンピュータ ネットワークおよび通信

フィンガープリント

「Power Analysis of Directly-connected FPGA Clusters」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル