Power consumption of hybrid circuits of single-electron transistors and complementary metal-oxide-semiconductor field-effect transistors

Ken Uchida, Junji Koga, Ryuji Oha, Akira Toriumi

    研究成果: Article査読

    5 被引用数 (Scopus)

    抄録

    The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complemen-tary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

    本文言語English
    ページ(範囲)1066-1070
    ページ数5
    ジャーナルIEICE Transactions on Electronics
    E84-C
    8
    出版ステータスPublished - 2001 8

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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