Power reduction of chip multi-processors using shared resource control cooperating with DVFS

Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can be reduced without violating real-time constraints by dynamic voltage and frequency scaling (DVFS), the clock frequency of each PU cannot be determined independently because of the performance impact caused by the conflict for the shared resources. To minimize power consumption in this situation, we first derive an analytical model which provides the optimal priority and clock frequency setting, and then propose a method of controlling the priority of shared resource accesses in cooperation with DVFS. From the analytical model, in dual-core CMPs, we reveal that the total power consumption is minimized when the clock frequency of two PUs becomes the same. An experiment with a synthetic benchmark supports the validity of the analytical model and the evaluation results with real applications show that the proposed method reduces the power consumption by up to 15% and 6.7% on average compared with a conventional DVFS technique.

本文言語English
ホスト出版物のタイトル2007 IEEE International Conference on Computer Design, ICCD 2007
ページ615-622
ページ数8
DOI
出版ステータスPublished - 2007
外部発表はい
イベント2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
継続期間: 2007 10月 72007 10月 10

出版物シリーズ

名前2007 IEEE International Conference on Computer Design, ICCD 2007

Conference

Conference2007 IEEE International Conference on Computer Design, ICCD 2007
国/地域United States
CityLake Tahoe, CA
Period07/10/707/10/10

ASJC Scopus subject areas

  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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