Power reduction techniques for dynamically reconfigurable processor arrays

T. Nishimura, K. Hirai, Y. Saito, T. Nakamura, Y. Hasegawa, S. Tsutsusmi, V. Tunbunheng, H. Amano

研究成果: Conference contribution

18 被引用数 (Scopus)

抄録

The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfiguration power. Evaluation result shows that processing power for PEs is dominant and reconfiguration power is about 20.7% of the total dynamic power consumption. Based on the above evaluation results, we proposed two dynamic power reduction techniques: functional unit-level operand isolation and selective context fetch. Evaluation results demonstrate that the functional unit-level operand isolation can reduce up to 20.8% of the dynamic power with only 2.2% area overhead. On the selective context fetch, the power reduction is limited by the increasing of the additional hardware.

本文言語English
ホスト出版物のタイトルProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
ページ305-310
ページ数6
DOI
出版ステータスPublished - 2008 11 3
イベント2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
継続期間: 2008 9 82008 9 10

出版物シリーズ

名前Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
国/地域Germany
CityHeidelberg
Period08/9/808/9/10

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

フィンガープリント

「Power reduction techniques for dynamically reconfigurable processor arrays」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル