Practical methodology of post-layout gate sizing for 15% more power saving

Noriyuki Miura, Naoki Kato, Tadahiro Kuroda

    研究成果: Paper査読

    1 被引用数 (Scopus)

    抄録

    This paper presents a practical methodology of post-layout gate sizing for power reduction. Wire capacitance presumed in logic synthesis typically contains excessive margin for better timing closure in layout design. Power waste due to this can be reduced by post-layout gate sizing based on information obtained by backannotation. In this paper, we discuss a theory of optimal gate sizing in a signal path with surplus timing. We also, propose a practical design methodology where standard cells are reselected from a cell library by the theory, replaced by engineering change order, and timing constraints are verified by a static timing analyzer. We have applied the methodology to a 700k-gate commercial application processor for 3G cellular phones. Even though the original design was optimized for 133MHz, 170mW operation in a 0.18μm CMOS technology, power dissipation was further squeezed by 15% in combinational logic without compromising the performance.

    本文言語English
    ページ434-437
    ページ数4
    出版ステータスPublished - 2004 6月 1
    イベントProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
    継続期間: 2004 1月 272004 1月 30

    Other

    OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
    国/地域Japan
    CityYokohama
    Period04/1/2704/1/30

    ASJC Scopus subject areas

    • コンピュータ サイエンスの応用
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 電子工学および電気工学

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