Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948μs. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.

本文言語English
ホスト出版物のタイトルIWIA 2005
ホスト出版物のサブタイトルInnovative Architecture for Future Generation High-Performance Processors and Systems
出版社IEEE Computer Society
ページ9-17
ページ数9
ISBN(印刷版)0769524834, 9780769524832
DOI
出版ステータスPublished - 2005
イベントIWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems - Oahu, HI, United States
継続期間: 2005 1月 172005 1月 19

出版物シリーズ

名前Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
2005
ISSN(印刷版)1537-3223

Other

OtherIWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems
国/地域United States
CityOahu, HI
Period05/1/1705/1/19

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)

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