This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.
|出版ステータス||Published - 1994|
|イベント||Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA|
継続期間: 1994 10月 10 → 1994 10月 12
|Other||Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors|
|City||Cambridge, MA, USA|
|Period||94/10/10 → 94/10/12|
ASJC Scopus subject areas