PROTEUS: Programmable hardware for telecommunication systems

N. Ohta, H. Nakada, K. Yamada, A. Tsutsui, T. Miyazaki

研究成果: Paper査読

15 被引用数 (Scopus)

抄録

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.

本文言語English
ページ178-183
ページ数6
出版ステータスPublished - 1994 12 1
イベントProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
継続期間: 1994 10 101994 10 12

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period94/10/1094/10/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

フィンガープリント 「PROTEUS: Programmable hardware for telecommunication systems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル