Proximity inter-chip communication

Tadahiro Kuroda

    研究成果: Conference contribution

    1 引用 (Scopus)

    抜粋

    A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm. CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

    元の言語English
    ホスト出版物のタイトルICSICT-2006
    ホスト出版物のサブタイトル2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    出版者IEEE Computer Society
    ページ1841-1844
    ページ数4
    ISBN(印刷物)1424401615, 9781424401611
    DOI
    出版物ステータスPublished - 2006 1 1
    イベントICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
    継続期間: 2006 10 232006 10 26

    出版物シリーズ

    名前ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Other

    OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
    China
    Shanghai
    期間06/10/2306/10/26

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    フィンガープリント Proximity inter-chip communication' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Kuroda, T. (2006). Proximity inter-chip communication. : ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 1841-1844). [4098558] (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). IEEE Computer Society. https://doi.org/10.1109/ICSICT.2006.306462