QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

    研究成果: Conference contribution

    58 被引用数 (Scopus)

    抄録

    A key consideration for deep neural network (DNN) inference accelerators is the need for large and high-bandwidth external memories. Although an architectural concept for stacking a DNN accelerator with DRAMs has been proposed previously, long DRAM latency remains problematic and limits the performance [1]. Recent algorithm-level optimizations, such as network pruning and compression, have shown success in reducing the DNN memory size [2]; however, since networks become irregular and sparse, they induce an additional need for agile random accesses to the memory systems.

    本文言語English
    ホスト出版物のタイトル2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ216-218
    ページ数3
    ISBN(電子版)9781509049394
    DOI
    出版ステータスPublished - 2018 3 8
    イベント65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
    継続期間: 2018 2 112018 2 15

    出版物シリーズ

    名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    61
    ISSN(印刷版)0193-6530

    Other

    Other65th IEEE International Solid-State Circuits Conference, ISSCC 2018
    国/地域United States
    CitySan Francisco
    Period18/2/1118/2/15

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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