RAM-based hardware accelerator for network data anonymization

Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

本文言語English
ホスト出版物のタイトルConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9783000446450
DOI
出版ステータスPublished - 2014 10 16
イベント24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany
継続期間: 2014 9 12014 9 5

出版物シリーズ

名前Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Other

Other24th International Conference on Field Programmable Logic and Applications, FPL 2014
国/地域Germany
CityMunich
Period14/9/114/9/5

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • ハードウェアとアーキテクチャ

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