Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

H. Tanaka; A. Hasegawa; S. Haruyama

doi:10.1049/el:20010051

Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

H. Tanaka, A. Hasegawa, S. Haruyama

研究成果: Article › 査読

2 被引用数 (Scopus)

抄録

A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.

本文言語	English
ページ（範囲）	77-78
ページ数	2
ジャーナル	Electronics Letters
巻	37
号	2
DOI	https://doi.org/10.1049/el:20010051
出版ステータス	Published - 2001 1月 18
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1049/el:20010051

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Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

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