Reconfigurable systolic Viterbi decoder

Kazuya Takahashi, Hiroshi Tobita, Shinnichiro Haruyama, Masao Nakagawa

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper introduces a new algorithm which saves the power consumption of the systolic Viterbi decoder. The new algorithm dynamically changes the trucated path length of a Viterbi decoder according to the channel condition, resulting in reduction of power consumption. This algorithm is based on the observation that the truncated path length and bit error rate are closely related. If we set the truncated path length short, we can reduce the size of the decoder even though the system performance is sacrificed. We propose reconfiguration of the truncated path length according to channel state. It is shown that power consumption of a systolic Viterbi decoder with convolutional code for a constraint length K = 3 and a code rate R = 1/2 can be eliminated over 20 percent at the bit error rate of 10-3 in a Rayleigh fading channel. Furthermore, the longer the truncated path length becomes, the more effective the proposed method is.

本文言語English
ホスト出版物のタイトルIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall
ページ1629-1632
ページ数4
3
DOI
出版ステータスPublished - 1999 12月 1
イベントIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall - Amsterdam, Netherlands
継続期間: 1999 9月 191999 9月 22

出版物シリーズ

名前IEEE Vehicular Technology Conference
番号3
50
ISSN(印刷版)1550-2252

Other

OtherIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall
国/地域Netherlands
CityAmsterdam
Period99/9/1999/9/22

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学
  • 応用数学

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