Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Masayuki Kimura, Kazuei Hironaka, Hideharu Amano

研究成果: Conference contribution

抄録

A power-consumption-centric assignment algorithm called partially fixed configuration mapping (PFCM) is proposed for multi-context dynamically reconfigurable processors. By assigning the same operations into the same PE (processing element) as many as possible, the amount of changing configuration data for dynamic reconfiguration can be reduced, resulting in the redundant power consumed for changing the configuration also being reduced. The proposed algorithm was implemented in a compiler for a dynamically reconfigurable processor for research. Evaluation results showed that the consumed power was reduced by 10% on average without increasing the execution time.

元の言語English
ホスト出版物のタイトル2011 International Conference on Field-Programmable Technology, FPT 2011
DOI
出版物ステータスPublished - 2011
イベント2011 International Conference on Field-Programmable Technology, FPT 2011 - New Delhi, India
継続期間: 2011 12 122011 12 14

Other

Other2011 International Conference on Field-Programmable Technology, FPT 2011
India
New Delhi
期間11/12/1211/12/14

Fingerprint

Parallel processing systems
Reconfiguration
Configuration
Dynamic Reconfiguration
Electric power utilization
Compiler
Execution Time
Power Consumption
Assignment
Processing
Evaluation

ASJC Scopus subject areas

  • Computational Mathematics

これを引用

Kimura, M., Hironaka, K., & Amano, H. (2011). Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. : 2011 International Conference on Field-Programmable Technology, FPT 2011 [6132707] https://doi.org/10.1109/FPT.2011.6132707

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. / Kimura, Masayuki; Hironaka, Kazuei; Amano, Hideharu.

2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132707.

研究成果: Conference contribution

Kimura, M, Hironaka, K & Amano, H 2011, Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. : 2011 International Conference on Field-Programmable Technology, FPT 2011., 6132707, 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, 11/12/12. https://doi.org/10.1109/FPT.2011.6132707
Kimura M, Hironaka K, Amano H. Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. : 2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132707 https://doi.org/10.1109/FPT.2011.6132707
Kimura, Masayuki ; Hironaka, Kazuei ; Amano, Hideharu. / Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. 2011 International Conference on Field-Programmable Technology, FPT 2011. 2011.
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