Reduction calculator in an FPGA based switching Hub for high performance clusters

Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

Unused logic in the field-programmable gate array (FPGA) for the switching hub is one potential resource to accelerate the computation of data exchanged through the hub. However, for large scale scientific computation, it is difficult to implement such an accelerator on the FPGA used in high performance computers. Here, a reduction calculator for executing ARGOT (accelerated radiative transfer on grids using oct-tree) to solve the radiative transfer equation used for simulation of astronomical objects is implemented on the FPGA of PEACH2 (PCI Express Adaptive Communication Hub ver2), a low latency switching hub for high performance GPU (graphics processor unit) clusters. The implemented reduction calculator uses a pipelined tree of adders and works with a 150-MHz clock without affecting the switching hub functions. Use of the DMA (direct memory access) transfer with descriptors made it possible to improve the performance of CPU excution by a maximum of about 45 times in a real system.

本文言語English
ホスト出版物のタイトル25th International Conference on Field Programmable Logic and Applications, FPL 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)9780993428005
DOI
出版ステータスPublished - 2015 10月 7
イベント25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom
継続期間: 2015 9月 22015 9月 4

Other

Other25th International Conference on Field Programmable Logic and Applications, FPL 2015
国/地域United Kingdom
CityLondon
Period15/9/215/9/4

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 信号処理
  • ソフトウェア
  • コンピュータ サイエンスの応用

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