RHiNET-3/SW: An 80-Gbit/s high-speed network switch for distributed parallel computing

S. Nishimura, T. Kudoh, H. Nishi, J. Yamamoto, R. Ueno, K. Harasawa, S. Fukuda, Y. Shikichi, S. Akutsu, K. Tasho, H. Amano

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

We have developed a prototype network switch, RHiNET-3/SW, for a RHiNET high-performance distributed parallel computing environment. It has eight I/O ports and each port provides high-speed, bi-directional 10-Gbit/s-per-port parallel optical data transmission in a distance of over 300 m. The aggregate throughput is 80 Gbit/s per board. A switch consists of a one-chip CMOS ASIC 8x8 switch LSI (SW-LSI; a 784-pin BGA package), four deskew LSIs, and eight pairs of 1.25-Gbit/s x 12-channel optical interconnection modules on a single board. The switch uses a hop-by-hop retransmission mechanism and credit-based flow control to provide reliable and long-transmission-distance data communication. The deskew LSI has a skew compensation function for 10-bit parallel data channels and an 8B10B encoder/decoder. Its optical transmitter modules use an 850-nm VCSEL and a 12-channel MMF (multi-mode fiber) ribbon. RHiNET-3/SW enables high-throughput. Long-distance and flexible-flow-control network communication by means of distributed parallel computing using commercial PCs.

本文言語English
ホスト出版物のタイトルHOT Interconnects 9, HIS 2001
出版社Institute of Electrical and Electronics Engineers Inc.
ページ119-123
ページ数5
ISBN(電子版)0769513573
DOI
出版ステータスPublished - 2001 1 1
イベントSymposium on High Performance Interconnects: HOT Interconnects 9, HIS 2001 - Stanford, United States
継続期間: 2001 8 222001 8 24

出版物シリーズ

名前Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects
2001-January
ISSN(印刷版)1550-4794

Other

OtherSymposium on High Performance Interconnects: HOT Interconnects 9, HIS 2001
国/地域United States
CityStanford
Period01/8/2201/8/24

ASJC Scopus subject areas

  • 工学(全般)

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