Run-time power gating of on-chip routers using look-ahead routing

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang

研究成果: Conference contribution

72 被引用数 (Scopus)

抄録

Since on-chip routers in Network-on-Chips play a key role in on-chip communication between cores, they should be always preparing for packet injections even if a part of cores are in standby mode, resulting in a larger standby power of routers compared with cores. The run-time power gating of individual channels in a router is one of attractive solutions to reduce the standby power of chip without affecting the on-chip communication. However, a state transition between sleep and active mode incurs the performance penalty, and turning a power switch on or off dissipates the overhead energy, which means a short-term sleep adversely increases the power consumption. In this paper, we propose a sleep control method based on look-ahead routing that detects the arrival of packets two hops ahead, so as to hide the wake-up delay and reduce the short-term sleeps of channels. Simulation results using real application traces show that the proposed method conceals the wake-up delay of less than five cycles, and more leakage power can be saved compared with the original naive method.

本文言語English
ホスト出版物のタイトル2008 Asia and South Pacific Design Automation Conference, ASP-DAC
ページ55-60
ページ数6
DOI
出版ステータスPublished - 2008
イベント2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
継続期間: 2008 3月 212008 3月 24

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
国/地域Korea, Republic of
CitySeoul
Period08/3/2108/3/24

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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