Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki; N. Yamanaka; K. Okazaki; Y. Ohtomo

doi:10.1049/el:19990428

Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki, N. Yamanaka, K. Okazaki, Y. Ohtomo

研究成果: Article › 査読

抄録

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

本文言語	English
ページ（範囲）	715-716
ページ数	2
ジャーナル	Electronics Letters
巻	35
号	9
DOI	https://doi.org/10.1049/el:19990428
出版ステータス	Published - 1999 4月 29
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1049/el:19990428

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abstract = "A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.",

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AU - Ohtomo, Y.

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Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

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