Scalable deep neural network accelerator cores with cubic integration using through chip interface

Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

本文言語English
ホスト出版物のタイトルProceedings - International SoC Design Conference 2017, ISOCC 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ155-156
ページ数2
ISBN(電子版)9781538622858
DOI
出版ステータスPublished - 2018 5 29
イベント14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
継続期間: 2017 11 52017 11 8

出版物シリーズ

名前Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

フィンガープリント 「Scalable deep neural network accelerator cores with cubic integration using through chip interface」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル