抄録
A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 2117-2118 |
| ページ数 | 2 |
| ジャーナル | Electronics Letters |
| 巻 | 35 |
| 号 | 24 |
| DOI | |
| 出版ステータス | Published - 1999 11月 25 |
| 外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学