MOS memory device with silicon nano-crystals based floating gate on very narrow channel has been fabricated. Large threshold voltage shifts of up to 1 V are obtained by applying small electric field to the tunneling oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.
|出版ステータス||Published - 1998|
|イベント||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China|
継続期間: 1998 10月 21 → 1998 10月 23
|Other||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology|
|Period||98/10/21 → 98/10/23|
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