Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics

Y. Shi, S. L. Gu, X. L. Yuan, Y. D. Zheng, K. Saito, H. Ishikuro, T. Hiramoto

研究成果: Paper査読

8 被引用数 (Scopus)

抄録

MOS memory device with silicon nano-crystals based floating gate on very narrow channel has been fabricated. Large threshold voltage shifts of up to 1 V are obtained by applying small electric field to the tunneling oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.

本文言語English
ページ838-841
ページ数4
出版ステータスPublished - 1998
外部発表はい
イベントProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China
継続期間: 1998 10 211998 10 23

Other

OtherProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology
CityBeijing, China
Period98/10/2198/10/23

ASJC Scopus subject areas

  • 工学(全般)

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