Skywalk: A topology for HPC networks with low-delay switches

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

With low-delay switches on the horizon, end-to-end latency in large-scale High Performance Computing (HPC) interconnects will be dominated by cable delays. In this context we define a new network topology, Skywalk, for deploying low-latency interconnects in upcoming HPC systems. Skywalk uses randomness to achieve low latency, but does so in a way that accounts for the physical layout of the topology so as to lead to further cable length and thus latency reductions. Via graph analysis and discrete-event simulation we show that Skywalk compares favorably (in terms of latency, cable length, and throughput) to traditional low-degree torus and moderate-degree hypercube topologies, to high-degree fully-connected Dragonfly topologies, to the HyperX topology, and to recently proposed fully random topologies.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 28th International Parallel and Distributed Processing Symposium, IPDPS 2014
出版社IEEE Computer Society
ページ263-272
ページ数10
ISBN(印刷版)9780769552071
DOI
出版ステータスPublished - 2014
イベント28th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2014 - Phoenix, AZ, United States
継続期間: 2014 5 192014 5 23

出版物シリーズ

名前Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS
ISSN(印刷版)1530-2075
ISSN(電子版)2332-1237

Other

Other28th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2014
CountryUnited States
CityPhoenix, AZ
Period14/5/1914/5/23

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

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