TY - JOUR
T1 - SoC architecture synthesis methodology based on high-level IPs
AU - Muraoka, Michiaki
AU - Nishi, Hiroaki
AU - Morizawa, Rafael K.
AU - Yokota, Hideaki
AU - Onishi, Yoichi
PY - 2004/12
Y1 - 2004/12
N2 - We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.
AB - We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.
KW - Architecture synthesis
KW - CAD
KW - High level IP
KW - System level design
UR - http://www.scopus.com/inward/record.url?scp=11144321517&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=11144321517&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:11144321517
VL - E87-A
SP - 3057
EP - 3067
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -