SoC architecture synthesis methodology based on high-level IPs

Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Yoichi Onishi

研究成果: Article査読

1 被引用数 (Scopus)

抄録

We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.

本文言語English
ページ(範囲)3057-3067
ページ数11
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E87-A
12
出版ステータスPublished - 2004 12
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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