SOI tri-gate nanowire MOSFETs for ultra-low power LSI

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Ken Uchida, Toshinori Numata

    研究成果: Conference contribution

    2 引用 (Scopus)

    抜粋

    Nanowire transistors (NW Tr.) are very promising for ultralow-power LSI [1-3]. However, Ion of reported 10nm-size NW Tr., essential for 10nm-Lg scaling, is relatively low due to large parasitic resistance (RSD) and immature performance boosters. Also, dynamic power control using substrate bias (Vsub) and circuit performance under low-V dd operation have not been sufficiently explored yet in NW Tr.

    元の言語English
    ホスト出版物のタイトル2012 IEEE International SOI Conference, SOI 2012
    DOI
    出版物ステータスPublished - 2012 12 1
    イベント2012 IEEE International SOI Conference, SOI 2012 - Napa, CA, United States
    継続期間: 2012 10 12012 10 4

    出版物シリーズ

    名前Proceedings - IEEE International SOI Conference
    ISSN(印刷物)1078-621X

    Other

    Other2012 IEEE International SOI Conference, SOI 2012
    United States
    Napa, CA
    期間12/10/112/10/4

      フィンガープリント

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    これを引用

    Saitoh, M., Ota, K., Tanaka, C., Uchida, K., & Numata, T. (2012). SOI tri-gate nanowire MOSFETs for ultra-low power LSI. : 2012 IEEE International SOI Conference, SOI 2012 [6404396] (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2012.6404396