Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

Toshinori Numata, Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

    本文言語English
    ホスト出版物のタイトルICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    ページ37-40
    ページ数4
    DOI
    出版ステータスPublished - 2010 12月 1
    イベント2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
    継続期間: 2010 11月 12010 11月 4

    出版物シリーズ

    名前ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Other

    Other2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
    国/地域China
    CityShanghai
    Period10/11/110/11/4

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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