Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Chika Tanaka, Masumi Saitoh, Kensuke Ota, Ken Uchida, Toshinori Numata

    研究成果: Conference contribution

    4 被引用数 (Scopus)

    抄録

    An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.

    本文言語English
    ホスト出版物のタイトルESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
    ページ159-162
    ページ数4
    DOI
    出版ステータスPublished - 2011 12 12
    イベント41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland
    継続期間: 2011 9 122011 9 16

    出版物シリーズ

    名前European Solid-State Device Research Conference
    ISSN(印刷版)1930-8876

    Other

    Other41st European Solid-State Device Research Conference, ESSDERC 2011
    CountryFinland
    CityHelsinki
    Period11/9/1211/9/16

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

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