Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima

研究成果: Conference contribution

33 被引用数 (Scopus)

抄録

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

本文言語English
ホスト出版物のタイトルProceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
編集者O. Diessel, J. Williams
ページ137-144
ページ数8
出版ステータスPublished - 2004 12 1
イベント2004 IEEE International Conference on Field-Programmable Technology, FPT '04 - Brisbane, Australia
継続期間: 2004 12 62004 12 8

出版物シリーズ

名前Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Other

Other2004 IEEE International Conference on Field-Programmable Technology, FPT '04
国/地域Australia
CityBrisbane
Period04/12/604/12/8

ASJC Scopus subject areas

  • 工学(全般)

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