Substrate noise influence on circuit performance in variable threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai

研究成果: Paper査読

8 被引用数 (Scopus)

抄録

This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well. A 2mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3V to above 3V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100kΩ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.

本文言語English
ページ309-312
ページ数4
出版ステータスPublished - 1996 12 1
外部発表はい
イベントProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
継続期間: 1996 8 121996 8 14

Other

OtherProceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period96/8/1296/8/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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