Superpixel accelerator for computer vision applications on arria 10 SoC

Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Noda Hiroyuki, Hideharu Amano

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.

本文言語English
ホスト出版物のタイトルProceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ55-60
ページ数6
ISBN(電子版)9781538657546
DOI
出版ステータスPublished - 2018 7月 11
イベント21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 - Budapest, Hungary
継続期間: 2018 4月 252018 4月 27

出版物シリーズ

名前Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018

Other

Other21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
国/地域Hungary
CityBudapest
Period18/4/2518/4/27

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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