Symbol-rate clock recovery for integrating DFE receivers

Tsutomu Takeya, Tadahiro Kuroda

    研究成果: Article査読

    抄録

    In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.

    本文言語English
    ページ(範囲)705-712
    ページ数8
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E96-A
    3
    DOI
    出版ステータスPublished - 2013 3

    ASJC Scopus subject areas

    • 信号処理
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 電子工学および電気工学
    • 応用数学

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