SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project

Ryuichi Takahashi, Yoshiyasu Takefuji

研究成果: Conference contribution

抄録

SystemVerilog assertion (SVA) is a way to express properties that are expected to be true in a design described in Verilog HDL IEEE1364 standard. We have already reported that legitimate peripheral participation (LPP) works very well for the fine grain microprocessor design education on FPGA where the heart of the system is chosen as the way-in which is the first step for the observation in LPP. We have demonstrated its effectiveness on superscalar design education, while the prior pipeline design education failed. The failure was caused by the top down design methodology guided in the education for the pipelining which appeared to be too difficult. Appropriate scheme to observe the heart of the pipelining is needed. We have found that SVA plays a key role where two senior students succeeded to design pipelined RISC having 3 stages and pipelined CISC having 4 stages in 2 months. White box test by using SVA enables the two senior students to observe the heart of the pipelining very effectively.

本文言語English
ホスト出版物のタイトル2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
ページ112-113
ページ数2
DOI
出版ステータスPublished - 2011 8 10
イベント2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011 - San Diego, CA, United States
継続期間: 2011 6 52011 6 6

出版物シリーズ

名前2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011

Other

Other2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
国/地域United States
CitySan Diego, CA
Period11/6/511/6/6

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 教育

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