Task level pipelining on multiple accelerators via FPGA switch

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku

研究成果: Paper査読

抄録

We show a task level pipelining on multiple accelerators with PEACH2. PEACH2, which is implemented on FPGA, enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level parallelism. Furthermore, we can process multiple task on multiple accelerators in a pipelined manner. In our evaluation, pipelined application which is implemented in a task level pipelined manner achieves 52% speed up compared to a single GPU.

本文言語English
ページ267-274
ページ数8
DOI
出版ステータスPublished - 2014
イベント12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014 - Innsbruck, Austria
継続期間: 2014 2 172014 2 19

Other

Other12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014
国/地域Austria
CityInnsbruck
Period14/2/1714/2/19

ASJC Scopus subject areas

  • ソフトウェア

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