Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.

本文言語English
ホスト出版物のタイトルFPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
ページ466-469
ページ数4
DOI
出版ステータスPublished - 2013 12月 1
イベント2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan
継続期間: 2013 12月 92013 12月 11

出版物シリーズ

名前FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Other

Other2013 12th International Conference on Field-Programmable Technology, FPT 2013
国/地域Japan
CityKyoto
Period13/12/913/12/11

ASJC Scopus subject areas

  • ソフトウェア

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