The impact of routing cache on high-performance switches

Michihiro Koibuchi, Shin Ichi Ishida, Hiroaki Nishi

研究成果: Conference contribution

抄録

Large parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computer systems. Switch delay dominates network latencies, especially for a large number of small transfer data. To reduce the network latencies, we exploit routing cache on a switch. Routing decision based on off-chip CAM(Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits. Our simulation results showed that 1,024-entry routing cache improves not only up to 13% of packet latency but also up to 18% of network throughput compared with no-cache switches.

本文言語English
ホスト出版物のタイトル10th International Conference on Optical Internet, COIN 2012
ページ40-41
ページ数2
出版ステータスPublished - 2012 9 28
イベント10th International Conference on Optical Internet, COIN 2012 - Yokohama, Kanagawa, Japan
継続期間: 2012 5 292012 5 31

出版物シリーズ

名前10th International Conference on Optical Internet, COIN 2012

Other

Other10th International Conference on Optical Internet, COIN 2012
CountryJapan
CityYokohama, Kanagawa
Period12/5/2912/5/31

ASJC Scopus subject areas

  • Computer Networks and Communications

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