Thermal-aware CMOS: Challenges for future technology and design evolutions

Ken Uchida, Tsunaki Takahashi

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.

    本文言語English
    ホスト出版物のタイトル2016 46th European Solid-State Device Research Conference, ESSDERC 2016
    出版社Editions Frontieres
    ページ150-153
    ページ数4
    ISBN(電子版)9781509029693
    DOI
    出版ステータスPublished - 2016 10月 18
    イベント46th European Solid-State Device Research Conference, ESSDERC 2016 - Lausanne, Switzerland
    継続期間: 2016 9月 122016 9月 15

    出版物シリーズ

    名前European Solid-State Device Research Conference
    2016-October
    ISSN(印刷版)1930-8876

    Other

    Other46th European Solid-State Device Research Conference, ESSDERC 2016
    国/地域Switzerland
    CityLausanne
    Period16/9/1216/9/15

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • 安全性、リスク、信頼性、品質管理

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