Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

Kensuke Ota, Masumi Saitoh, Yukio Nakabayashi, Takamitsu Ishihara, Toshinori Numata, Ken Uchida

    研究成果: Conference contribution

    3 被引用数 (Scopus)

    抄録

    Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.

    本文言語English
    ホスト出版物のタイトル2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
    ページ134-137
    ページ数4
    DOI
    出版ステータスPublished - 2010 12 15
    イベント2010 European Solid State Device Research Conference, ESSDERC 2010 - Sevilla, Spain
    継続期間: 2010 9 142010 9 16

    出版物シリーズ

    名前2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

    Other

    Other2010 European Solid State Device Research Conference, ESSDERC 2010
    CountrySpain
    CitySevilla
    Period10/9/1410/9/16

    ASJC Scopus subject areas

    • Condensed Matter Physics

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