Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor

Negative bias temperature instability in Si (100) and (110) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) is systematically studied. Threshold voltage shift in (110) pMOSFETs is found to be larger than that in (100) pMOSFETs because of larger amount of the generated interface traps. On the other hand, mechanisms behind the generation of the interface traps are independent of the surface orientations. We newly found that drain current degradation in (110) pMOSFETs is severer than that in (100) pMOSFETs even when the same amount of charges is generated at the interface. This can be explained by larger mobility degradation in (110) pMOSFETs.