Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor

K. Ota, M. Saitoh, Y. Nakabayashi, T. Ishihara, K. Uchida, T. Numata

    研究成果: Article査読

    3 被引用数 (Scopus)

    抄録

    Negative bias temperature instability in Si (100) and (110) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) is systematically studied. Threshold voltage shift in (110) pMOSFETs is found to be larger than that in (100) pMOSFETs because of larger amount of the generated interface traps. On the other hand, mechanisms behind the generation of the interface traps are independent of the surface orientations. We newly found that drain current degradation in (110) pMOSFETs is severer than that in (100) pMOSFETs even when the same amount of charges is generated at the interface. This can be explained by larger mobility degradation in (110) pMOSFETs.

    本文言語English
    論文番号212109
    ジャーナルApplied Physics Letters
    100
    21
    DOI
    出版ステータスPublished - 2012 5月 21

    ASJC Scopus subject areas

    • 物理学および天文学(その他)

    フィンガープリント

    「Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル