A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 2000 12月 1|
|イベント||2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States|
継続期間: 2000 12月 10 → 2000 12月 13
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