Throughput enhancement strategy of maskless electron beam direct writing for logic device

R. Inanami, S. Magoshi, S. Kousai, M. Hamada, T. Takayanagi, K. Sugihara, K. Okumura, T. Kuroda

研究成果: Conference article査読

36 被引用数 (Scopus)

抄録

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

本文言語English
ページ(範囲)833-836
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 2000 12月 1
外部発表はい
イベント2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
継続期間: 2000 12月 102000 12月 13

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学

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