Tightly-coupled multi-layer topologies for 3-D NoCs

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

67 被引用数 (Scopus)

抄録

Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length and wire delay. Although the network topology of 3-D NoC has been explored for a couple of years, there is still only a narrow range of choices. In this paper, we propose a class of 3-D topologies called Xbar-connected Network-on-Tiers (XNoTs), which consist of multiple network layers tightly connected via crossbar switches. To make the best use of the short delay and high density of inter-wafer links, XNoTs topologies have cross-bar switches that connect different layers and their cores. The planar topology on every layer can be independently customized so as to meet the cost-performance requirements, as far as network connectivity is at least guaranteed with the bottom layer. We also propose their routing algorithm, which guarantees deadlock-freedom by restricting the inter-layer packet transfer from a lower-numbered layer to a higher-numbered layer. Path sets at the bottom layer close to the heat sink of the chip can be selectively employed in order to mitigate the heat-dissipation problem of 3-D ICs. Several forms of XNoTs topologies including meshes, tori, and/or trees are created, and they are evaluated in terms of performance, cost, and energy consumption. As a result, we show that even with the flexibilities mentioned above, XNoTs achieve at least as high throughput as existing 3-D topologies for equivalent chip sizes.

本文言語English
ホスト出版物のタイトル2007 International Conference on Parallel Processing, ICPP
DOI
出版ステータスPublished - 2007
イベント36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
継続期間: 2007 9月 102007 9月 14

出版物シリーズ

名前Proceedings of the International Conference on Parallel Processing
ISSN(印刷版)0190-3918

Other

Other36th International Conference on Parallel Processing in Xi'an, ICPP
国/地域China
CityXi'an
Period07/9/1007/9/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 工学(全般)

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